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?2007 by catalyst semiconductor, inc. characteristics subject to change without notice 1 doc. no. 1106, rev. f cat93c46 1-kb microwire serial eeprom features high speed operation: 2mhz 1.8v to 5.5v supply voltage range selectable x8 or x16 memory organization self-timed write cycle with auto-clear software write protection power-up inadvertant write protection low power cmos technology 1,000,000 program/erase cycles 100 year data retention industrial temperature ranges rohs-compliant 8-pin pdip, soic, tssop and 8-pad tdfn packages pin configuration pdip (l) soic (v, x) tssop (y) tdfn (vp2) soic (w) description the cat93c46 is a 1k-bit serial eeprom memory device which is configured as either 64 registers of 16 bits (org pin at v cc ) or 128 registers of 8 bits (org pin at gnd). each register can be written (or read) serially by using the di (or do) pin. the cat93c46 features a self-timed internal write with auto-clear. on-chip power- on reset circuit protects the internal logic against powering up in the wrong state. functional symbol note: when the org pin is connected to vcc, the x16 organization is selected. when it is connected to ground, the x8 organization is selected. if the org pin is left unconnected, then an internal pullup device will select the x16 organization. cs sk di org do cat93c46 v cc gnd pin functions pin name function cs chip select sk clock input di serial data input do serial data output v cc power supply gnd ground org memory organization nc no connection 8 7 6 5 v cc nc org gnd di cs sk do 1 2 3 4 8 7 6 5 org gnd do di cs nc v cc sk 1 2 3 4 for ordering information details, see page 13.
cat93c46 2 doc no. 1106, rev. f ?200 7 by catalyst semiconductor, inc. characteristics subject to change without notice d.c. operating characteristics v cc = +1.8v to +5.5v, t a =-40 c to +85 c, unless otherwise specified. symbol parameter test conditions min max units i cc1 power supply current f sk = 1mhz 1 ma (write) v cc = 5.0v i cc2 power supply current f sk = 1mhz 500 a (read) v cc = 5.0v i sb1 power supply current v in =gnd or v cc, cs =gnd 2 a (standby) (x8 mode) org=gnd i sb2 power supply current v in =gnd or v cc, cs =gnd 1 a (standby) (x16mode) org=float or v cc i li input leakage current v in = gnd to v cc 1 a i lo output leakage current v out = gnd to v cc ,1 a cs = gnd v il1 input low voltage 4.5v v cc < 5.5v -0.1 0.8 v v ih1 input high voltage 4.5v v cc < 5.5v 2 v cc + 1 v v il2 input low voltage 1.8v v cc < 4.5v 0 v cc x 0.2 v v ih2 input high voltage 1.8v v cc < 4.5v v cc x 0.7 v cc +1 v v ol1 output low voltage 4.5v v cc < 5.5v 0.4 v i ol = 2.1ma v oh1 output high voltage 4.5v v cc < 5.5v 2.4 v i oh = -400 a v ol2 output low voltage 1.8v v cc < 4.5v 0.2 v i ol = 1ma v oh2 output high voltage 1.8v v cc < 4.5v v cc - 0.2 v i oh = -100 a notes: (1) stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and re liability. (2) the dc input voltage on any pin should not be lower than -0.5v or higher than v cc +0.5v. during transitions, the voltage on any pin may undershoot to no less than -1.5v or overshoot to no more than v cc +1.5v, for periods of less than 20 ns. (3) these parameters are tested initially and after a design or process change that affects the parameter according to appropriate aec-q100 and jedec test methods. (4) block mode, v cc = 5v, 25 c absolute maximum ratings (1) storage temperature -65 c to +150 c voltage on any pin with respect to ground (2) -0.5 v to +6.5 v reliability characteristics (3) lobmy sr etemara pn i ms tinu n dne )4( ecnarudn e0 00,000, 1s elcycesare/margorp t rd noitneterata d0 0 1s raey
cat93c46 3 doc no. 1106, rev. f ?200 7 by catalyst semiconductor, inc. characteristics subject to change without notice limits symbol parameter min max units t css cs setup time 50 ns t csh cs hold time 0 ns t dis di setup time 100 ns t dih di hold time 100 ns t pd1 output delay to 1 0.25 s t pd0 output delay to 0 0.25 s t hz (1) output delay to high-z 100 ns t ew program/erase pulse width 5 ms t csmin minimum cs low time 0.25 s t skhi minimum sk high time 0.25 s t sklow minimum sk low time 0.25 s t sv output delay to status valid 0.25 s sk max maximum clock frequency dc 2000 khz a.c. characteristics (2) v cc = +1.8v to +5.5v, t a =-40 c to +85 c, unless otherwise specified. pin capacitance t a =25 c, f=1mhz, v cc =5v symbol test conditions min typ max units c out (1) output capacitance (do) v out =0v 5 pf c in (1) input capacitance (cs, sk, di, org) v in =0v 5 pf notes: (1) these parameters are tested initially and after a design or process change that affects the parameter according to appropriate aec-q100 and jedec test methods. (2) test conditions according to ?c test conditions?table. (3) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. power-up timing (1)(3) symbol parameter max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms
cat93c46 4 doc no. 1106, rev. f ?200 7 by catalyst semiconductor, inc. characteristics subject to change without notice device operation the cat93c46 is a 1024-bit nonvolatile memory in- tended for use with industry standard microprocessors. the cat93c46 can be organized as either registers of 16 bits or 8 bits. when organized as x16, seven 9-bit instructions control the reading, writing and erase opera- tions of the device. when organized as x8, seven 10-bit instructions control the reading, writing and erase operations of the device. the cat93c46 operates on a single power supply and will generate on chip the high voltage required during any write operation. instructions, addresses, and write data are clocked into the di pin on the rising edge of the clock (sk). the do pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status during a write operation. the serial communication protocol follows the timing shown in figure 1. the ready/busy status can be determined after the start of internal write cycle by selecting the device (cs high) and polling the do pin; do low indicates that the write operation is not completed, while do high indicates that the device is ready for the next instruction. if necessary, the do pin may be placed back into a high impedance state during chip select by shifting a dummy ??into the di pin. the do pin will enter the high impedance state on the rising edge of the clock (sk). placing the do pin into the high impedance state is recommended in appli- cations where the di pin and the do pin are to be tied together to form a common di/o pin. the ready/busy instruction set noitcurtsn it ibtrat se docpo sserdd aa tad stnemmoc8 x6 1 x8 x6 1x dae r10 10 a-6 a0 a-5 a0 anasserddadaer esar e11 10 a-6 a0 a-5 a0 anasserddaraelc etir w11 00 a-6 a0 a-5 a0 d-7 d0 d-51 d0 anasserddaetirw new e10 0 xxxxx1 1x xxx11 elbaneetirw sdw e10 0 xxxxx0 0x xxx00 elbasidetirw lar e10 0 xxxxx0 1x xxx01 sesserddallaraelc lar w10 0 xxxxx1 0x xxx10 0d-7 d0 d-51 ds esserddallaetirw flag can be disabled only in ready state; no change is allowed in busy state. the format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit address (an additional bit when organized x8) and for write operations a 16-bit data field (8-bit for x8 organization). read upon receiving a read command (figure 2) and an address (clocked into the di pin), the do pin of the cat93c46 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (msb first). the output data bits will toggle on the rising edge of the sk clock and are stable after the specified time delay (t pd0 or t pd1 ). erase/write enable and disable the cat93c46 powers up in the write disable state. any writing after power-up or after an ewds (write disable) instruction must first be preceded by the ewen (write enable) instruction. once the write instruction is enabled, it will remain enabled until power to the device is removed, or the ewds instruction is sent. the ewds instruction can be used to disable all cat93c46 write and erase instructions, and will prevent any accidental writing or clearing of the device. data can be read normally from the device regardless of the write enable/disable status. the ewen and ewds instructions timing is shown in figure 3. a.c. test conditions input rise and fall times 50ns input pulse voltages 0.4v to 2.4v 4.5v v cc 5.5v timing reference voltages 0.8v, 2.0v 4.5v v cc 5.5v input pulse voltages 0.2v cc to 0.7v cc 1.8v v cc 4.5v timing reference voltages 0.5v cc 1.8v v cc 4.5v output load current source i olmax /i ohmax ; c l =100pf
cat93c46 5 doc no. 1106, rev. f ?200 7 by catalyst semiconductor, inc. characteristics subject to change without notice figure 1. sychronous data timing figure 2. read instruction timing sk di cs do t dis t pd0, t pd1 t csmin t css t dis t dih t skhi t csh valid valid data valid t sklow sk cs di do t csmin standby t hz high-z high-z 11 0 a n a n 1 a 0 0 d n d n 1 d 1 d 0 t pd0 figure 3. ewen/ewds instruction timing cs di standby 10 0 * * enable=11 disable=00 sk
cat93c46 6 doc no. 1106, rev. f ? 200 7 by catalyst semiconductor, inc. characteristics subject to change without notice write after receiving a write command (figure 4), address and the data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking for auto-clear and data store cycles on the memory location specified in the instruction. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c46 can be determined by selecting the device and polling the do pin. since this device features auto-clear before write, it is not necessary to erase a memory location before it is written into. erase upon receiving an erase command and address, the cs (chip select) pin must be deasserted for a minimum of t csmin (figure 5). the falling edge of cs will start the self clocking clear cycle of the selected memory location. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/ busy status of the cat93c46 can be determined by selecting the device and polling the do pin. once cleared, the content of a cleared location returns to a logical 1 state. erase all upon receiving an eral command (figure 6), the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking clear cycle of all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c46 can be determined by selecting the device and polling the do pin. once cleared, the contents of all memory bits return to a logical 1 state. write all upon receiving a wral command and data, the cs (chip select) pin must be deselected for a minimum of t csmin (figure 7). the falling edge of cs will start the self clocking data write to all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/ busy status of the cat93c46 can be determined by selecting the device and polling the do pin. it is not necessary for all memory locations to be cleared before the wral command is executed. figure 4. write instruction timing sk cs di do t csmin standby high-z high-z 101 a n a n-1 a 0 d n d 0 busy ready status verify t sv t hz t ew
cat93c46 7 doc no. 1106, rev. f ? 200 7 by catalyst semiconductor, inc. characteristics subject to change without notice figure 7. wral instruction timing figure 6. eral instruction timing sk cs di do standby t cs min high-z high-z 10 1 busy ready status verify t sv t hz t ew 00 status verify sk cs di do standby high-z 10 1 busy ready t sv t hz t ew t csmin d n d 0 00 figure 5. erase instruction timing sk cs di do standby high-z high-z 1 a n a n-1 busy ready status verify t sv t hz t ew t cs min 11 a 0
cat93c46 8 doc no. 1106, rev. f ? 200 7 by catalyst semiconductor, inc. characteristics subject to change without notice 8-lead 300 mil plastic dip (l) a e b e1 b2 l a2 a1 e d eb 24c16_8-lead_dip_(300p).eps symbol a a1 b b2 d e e1 e eb l min 0.38 0.36 9.02 7.62 6.09 6.35 7.87 0.115 0.130 0.150 nom 0.46 1.771.14 7.87 2.54 bsc max 4.57 a2 3.05 3.81 0.56 10.16 8.25 7.11 9.65 notes: 1. all dimensions are in millimeters. 2. complies with jedec standard ms001. 3. dimensioning and tolerancing per ansi y14.5m-1982 for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat93c46 9 doc no. 1106, rev. f ? 200 7 by catalyst semiconductor, inc. characteristics subject to change without notice 8-lead 150 mil soic (v, w) 24c16_8-lead_soic.eps symbol a1 a b c d e e1 h l min 0.10 1.35 0.33 4.80 5.80 3.80 0.25 0.40 nom 0.250.19 max 0.25 1.75 0.51 5.00 6.20 4.00 e 1 .27 bsc 0.50 1.27 10 8 e e1 d a1 e l 1 c b h x 45 a notes: 1. all dimensions are in millimeters. 2. complies with jedec specification ms-012. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat93c46 10 doc no. 1106, rev. f ? 200 7 by catalyst semiconductor, inc. characteristics subject to change without notice 8-lead 208 mil soic (x) notes: 1. all dimensions are in millimeters. 2. complies with eiaj specification edr-7320. 3. d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.06in per side. 4. e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.010in per side. 5. lead span/stand off height/coplanarity are considered as special characteristic (a1). l a1 a b e e d 1 c symbol a1 a b c d e e1 e l min 0.05 0.36 5.13 7.75 5.13 0.51 nom 0.250.19 1.27 bsc max 0.25 2.03 0.48 5.33 8.26 5.38 0.76 10 8 for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat93c46 11 doc no. 1106, rev. f ? 200 7 by catalyst semiconductor, inc. characteristics subject to change without notice 8-lead tssop (y) 8 5 1 4 e e1 e/2 pin #1 ident. d b l 1 e a a1 a2 see detail a see detail a seating plane c gage plane 0.25 symbol a a1 a2 b c d e e1 e l 1 min 0.05 0.80 0.09 2.90 6.30 6.4 4.30 0.00 8.00 nom 0.90 0.300.19 3.00 4.40 0.60 0.750.50 max 1.20 0.15 1.05 0.20 3.10 6.50 4.50 0.65 bsc notes: 1. all dimensions are in millimeters. 2. complies with jedec standard mo-153 for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat93c46 12 doc no. 1106, rev. f ? 200 7 by catalyst semiconductor, inc. characteristics subject to change without notice 8-pad tdfn 2x3 package (vp2) e2 a2 e pin 1 index area l tdfn2x3 ( 03 ) .e ps a3 pin 1 id e b a1 3 x e d2 d a symbol a a1 a2 a3 b d d2 e e2 e l min 0.70 0.00 0.45 0.20 1.90 1.30 1.40 2.90 1.20 0.20 0.30 0.40 nom 0.75 0.02 0.55 0.20 ref 0.25 2.00 3.00 0.50 typ max 0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.401.30 notes: 1. all dimensions are in millimeters. 2. complies with jedec specification mo-229. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat93c46 13 doc no. 1106, rev. f ? 200 7 by catalyst semiconductor, inc. characteristics subject to change without notice example of ordering information notes: (1) all packages are rohs-compliant (lead-free, halogen-free). (2) the standard lead finish for the soic, eiaj (x) package is matte-tin; the standard lead finish for all other packages is nip dau. (3) the device used in the above example is a cat93c46vi-gt3 (soic, jedec, industrial temperature, nipdau, tape & reel). (4) the soic, eiaj (x) package is available in reels of 2000 pcs/reel (i.e. cat93c46xi-t2). all other packages are offered in re els of 3000 pcs/reel. (5) for additional package and temperature options, please contact your nearest catalyst semiconductor sales office. prefix device # suffix 93c46 v i product number 93c46 cat temperature range i = industrial (-40 c - 85 c) optional company id package l = pdip v = soic, jedec w = soic, jedec x = soic, eiaj y = tssop vp2 = tdfn (2x3mm) tape & reel (4) t: tape & reel 2: 2000/reel 3: 3000/reel lead finish (2) blank: matte-tin g: nipdau t3 g
cat93c46 14 doc no. 1106, rev. f ? 200 7 by catalyst semiconductor, inc. characteristics subject to change without notice revision history eta dn oisive rs tnemmoc 50/10/2 1a e ussilaitini 50/80/2 1b s citsiretcarahcgnitarepoc.detadpu 60/22/2 0c n oitarugifnocnipetadpu nvereid,scitsiretarahc.c.aetadpu snoisnemidegakcapetadpu noitamrofnigniredroetadpu gnikramegakcapetadpu 60/42/5 0d n oitarugifnocnipetadpu snoitcnufnipetadpu scitsiretarahcgnitarepo.c.detadpu scitsiretarahc.c.aetadpu noitarepoecivedetadpu gnikramegakcapetadpu leerdnaepatevomer noitamrofniegakcapfoelpmaxeetadpu 60/10/8 0e s citsiretarahcgnitarepo.c.detadpu ecnaticapacniprofnoitidnoctsetetadpu scitsiretarahc.c.aetadpu noitarepoecivedetadpu egakcap)x(cioslim802dael8dda gnikramegakcapetadpu noitamrofniegakcapfoelpmaxeetadpu 70/80/2 0f s citsiretcarahcgnitarepo.c.detadpu scitsiretcarahc.c.aetadpu 6dna5serugifetadpu gnikramegakcapevomer
copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: ae2 , beyond memory , dpp , ezdim , minipot and quad-mode catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability arising out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semiconduct or product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. catalyst semiconductor, inc. corporate headquarters 2975 stender way santa clara, ca 95054 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com publication #: 1106 revison: e issue date: 02/08/07

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